An automatic memory backup circuit disclosed in Japanese Unexamined Patent Publication No. 2 (1990)-16384 (hereinafter “prior art”) includes a CPU, an I/O port connected to the CPU, five buffers, and other components. The first of the five buffers is connected to a multidata bus coupled to the I/O port output. The second buffer is connected to an output multidata bus of the first buffer. The third buffer is connected to an output multidata bus of the first buffer. A data memory having an address terminal is connected to a multiaddress bus coupled to the I/O port output. An address input terminal is coupled to the second buffer output. A backup memory having an address terminal is connected to a multiaddress bus coupled to the I/O port output. A data input terminal is connected to the third buffer output. The fourth buffer is connected to a data output terminal of the data memory. The fifth buffer is connected to the data output terminal of the backup memory, and its output is connected to the I/O port input with the fourth buffer output. The I/O port output is connected to the first to fifth buffers, and to the control terminals of the data memory and backup memory.
In such configuration of the automatic backup circuit, data can be simultaneously written to both RAM and EEPROM without resorting to the CPU. Further, by changing control setting of buffers and memories from the I/O port, the data can be loaded and saved by changing address buses without resorting to the CPU. However, the data memory and the backup memory are controlled individually by different control signals. From the output of the I/O port to the control terminals of the data memory and the backup memory, control lines are connected individually. Accordingly, the CPU must control the data memory and the backup memory individually, and further individually control the first to fifth buffers provided on the data bus. As a result, the control scheme may be complicated. Accordingly, it may require extra time to perform the simultaneous writing of the data memory and the backup memory using the automatic backup circuit disclosed in the prior art.
In addition, propagation time of data processed via the data bus must be controlled. The five buffers are necessary for the data bus to control the propagation time of the data in routing the data, thus adding to the complexity of the prior art circuit. Furthermore, the circuit configuration of the prior art may increase power consumption of the circuit as well as cause a delay in the data propagation.